A hexadecimal
B octal
C binary
D decimal
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A True
B False
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A hexadecimal
B binary
C octal
D decimal
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A True
B False
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A
False
B
True
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A
a conditioning circuit connected between a standard TTL NAND gate and a standard TTL OR gate
B
a circuit connected between the driver and load to condition a signal so that it is compatible with the load
C
any gate that is a TTL operational amplifier designed to condition signals between NMOS transistors
D
any TTL circuit that is an input buffer stage
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