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Directions to Solve

In the questions below the sentences have been given in Active/Passive voice. From the given alternatives, choose the one which best expresses the given sentence in Passive/Active voice.

Q1: He is said to be very rich.

A People say it is very rich.

B He said he is very rich.

C He said it is very rich.

D People say he is very rich.

Q2: Bitwise can be used to generate a random number.

A Yes

B No

Q3: Which of the examples below expresses the commutative law of multiplication?

A A • B = B • A

B A • (B • C) = (A • B) • C

C A + B = B + A

D A • B = B + A

Q4: The Boolean expression mcq19_1001_1.gif is logically equivalent to what single gate?

A AND

B OR

C NAND

D NOR

Q5: The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is referred to as:

A the associative law of multiplication

B the commutative law of addition

C DeMorgan's second theorem

D a Karnaugh map

Q6: The systematic reduction of logic circuits is accomplished by:

A TTL logic

B using a truth table

C symbolic reduction

D using Boolean algebra

Q7: Logically, the output of a NOR gate would have the same Boolean expression as a(n):

A NOR gate immediately followed by an INVERTER

B AND gate immediately followed by an INVERTER

C NAND gate immediately followed by an INVERTER

D OR gate immediately followed by an INVERTER

Q8: Which of the examples below expresses the distributive law of Boolean algebra?

A A • (B + C) = (A • B) + (A • C)

B (A + B) + C = A + (B + C)

C A • (B • C) = (A • B) + C

D A + (B + C) = (A • B) + (A • C)

Q9: Which output expression might indicate a product-of-sums circuit construction?

A mca19_1011a1.gif

B mca19_1011c1.gif

C mca19_1011d1.gif

D mca19_1011b1.gif

Q10: One of DeMorgan's theorems states that mcq19_1007_1.gif. Simply stated, this means that logically there is no difference between:

A a NAND gate and an OR gate with a bubbled output

B a NOR gate and an AND gate with a bubbled output

C a NOR gate and a NAND gate with a bubbled output

D a NAND gate and an AND gate with a bubbled output