- Digital Electronics - Section 1
- Digital Electronics - Section 2
- Digital Electronics - Section 3
- Digital Electronics - Section 4
- Digital Electronics - Section 5
- Digital Electronics - Section 6
- Digital Electronics - Section 7
- Digital Electronics - Section 8
- Digital Electronics - Section 9
- Digital Electronics - Section 10
- Digital Electronics - Section 11
- Digital Electronics - Section 12
- Digital Electronics - Section 13
- Digital Electronics - Section 14
- Digital Electronics - Section 15
- Digital Electronics - Section 16
- Digital Electronics - Section 17
- Digital Electronics - Section 18
- Digital Electronics - Section 19
- Digital Electronics - Section 20
- Digital Electronics - Section 21
- Digital Electronics - Section 22
- Digital Electronics - Section 23
- Digital Electronics - Section 24


Digital Electronics - Engineering
Q1: A 4 bit modulo 16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50 ns. The max. clock frequency that can be used is equal toA
20 MHz
B
10 MHz
C
5 MHz
D
4 MHz
ANS:C - 5 MHz Propagation Delay for one FF is 50 nsec. For 4 FF = 50 x 4 = 200 nsec. |


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