- Digital Electronics - Section 1
- Digital Electronics - Section 2
- Digital Electronics - Section 3
- Digital Electronics - Section 4
- Digital Electronics - Section 5
- Digital Electronics - Section 6
- Digital Electronics - Section 7
- Digital Electronics - Section 8
- Digital Electronics - Section 9
- Digital Electronics - Section 10
- Digital Electronics - Section 11
- Digital Electronics - Section 12
- Digital Electronics - Section 13
- Digital Electronics - Section 14
- Digital Electronics - Section 15
- Digital Electronics - Section 16
- Digital Electronics - Section 17
- Digital Electronics - Section 18
- Digital Electronics - Section 19
- Digital Electronics - Section 20
- Digital Electronics - Section 21
- Digital Electronics - Section 22
- Digital Electronics - Section 23
- Digital Electronics - Section 24


Digital Electronics - Engineering
Q1: For a MOD-12 counter, the FF has a tpd = 60 ns The NAND gate has a tpd of 25 n sec. The clock frequency isA
3.774 MHz
B
> 3.774 MHz
C
< 3.774 MHz
D
4.167 MHz
ANS:A - 3.774 MHz
For a proper working, the clock period should be equal to or greater than
tpd = Mod 12 - 4FFs = 4 x 60 = 240 nsec.
Total tpd = 240 + 25 = 265 nsec.
= fc ![]() |


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