If a signal passing through a gate is inhibited by sending a low into one of the inputs, and the output is HIGH, the gate is a(n):

ANS:B - NAND

Its is NAND gate but nt OR gate because:

NAND gate.
--------------

a b y

0 0 1 <---
0 1 1.
1 0 1.
1 1 o.

OR gate.
-----------

a b y.
0 0 0 <---
0 1 1.
1 0 1.
1 1 1.

If you observe both truth table you will get to know.

We are sending a low into one of the input and other may be one or zero but the output must be HIGH.

It's only in NANA GATE 111.