Digital Electronics

Q1: In a positive-edge-triggered JK flip-flop, a low J and a low K produce __________ state. A high __________ on the rising edge of the clock.

A inactive, reset

B active, reset

C active, toggle

D inactive, toggle

ANS:D - inactive, toggle

No answer description is available.



img not found
img

For help Students Orientation
Mcqs Questions

One stop destination for examination, preparation, recruitment, and more. Specially designed online test to solve all your preparation worries. Go wherever you want to and practice whenever you want, using the online test platform.