Analog Electronics - Engineering

Q1:

In following figure find VDSQ by assuming gate current is negligible for the p-channel JFET. (if IDQ = - 6 mA, RS = 0, VDD = -18 V, RD = 2 kΩ, IDSS = - 10 mA, IPO = - 3 V)

A 4 V

B - 6 V

C - 10 V

D 6 V

ANS:B - - 6 V

By Appling KVL around drain source loop. VDSQ = -18 - (-6). 2 x 103 = - 18 + 12 k x 10-3  -6 V.