Flip-Flops

The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and are HIGH. and PRE are LOW. What could be causing the problem?

A There is no problem.

B The clock should be held HIGH.

C The PRE is stuck LOW.

D The CLR is stuck HIGH.

ANS:C - The PRE is stuck LOW.

Preset and clear are asynchronous inputs to a flip-flop.

If the preset and clear are low it gives race around condition so, preset and clear should never below.
Preset is used to set the flip-flop to previous state ie,1.

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