Logic Gates

Q1:
The gates in this figure are implemented using TTL logic. If the input of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.

A a steady LOW

B a steady HIGH

C an undefined level

D pulses

ANS:A - a steady LOW

Answer is correct because. TTL is of negative logic so the input at inverter is open means it's high the output will be low so the and gate output is steady low.

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