Logic Gates

Q1:
The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.

A a steady LOW

B a steady HIGH

C an undefined level

D pulses

ANS:D - pulses

Doesn't 'open' mean no current in that wire i.e. HighZ, makes first input undriven.

Answer should be "an Undefined level".

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