A JTAG interface is a special interface added to a chip. Depending on the version of JTAG, two, four, or five pins are added.

The four and five-pin interfaces are designed so that multiple chips on board can have their JTAG lines daisy-chained together if specific conditions are met.

The two-pin interface is designed so that multiple chips can be connected in a star topology. In either case, a test probe need only connect to a single "JTAG port" to have access to all chips on a circuit board.

The connector pins are:
1. TDI (Test Data In)
2. TDO (Test Data Out)
3. TCK (Test Clock)
4. TMS (Test Mode Select)
5. TRST (Test Reset) optional.