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Flip-Flops and Timers

Q1: What is one disadvantage of an S-R flip-flop?

A It has no Enable input.

B It has a RACE condition.

C It has no clock input.

D It has only a single output.

ANS:B - It has a RACE condition.

Race around condition is the drawback of j-k flip flop not of s-r flip flop. The main drawback of s-r flip flop is invalid output when both the inputs are high. In j k flip flop, race around condition is explained as," when duration of input change is less than that of clock pulse, then we cannot get the proper output, as output feeds back to input in j k flip flop. to avoid this problem, master slave flip flop is invented."



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