Sequential Logic Circuits

Q1: What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?

A PIPO

B SISO

C SIPO

D PISO

Q2: Which type of device may be used to interface a parallel data format with external equipment's serial format?

A key matrix

B UART

C memory chip

D serial-in, parallel-out

Q3: A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

A shift register sequencer

B clock

C johnson

D binary

Q4: Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

A input clock pulses are applied only to the first and last stages

B input clock pulses are applied only to the last stage

C input clock pulses are not used to activate any of the counter stages

D input clock pulses are applied simultaneously to each stage

Q5: A ripple counter's speed is limited by the propagation delay of:

A each flip-flop

B all flip-flops and gates

C the flip-flops only with gates

D only circuit gates

Q6: The serial-in, parallel-out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.

A True

B False

Q7: A comparison between ring and johnson counters indicates that:

A a ring counter has fewer flip-flops but requires more decoding circuitry

B a ring counter has an inverted feedback path

C a johnson counter has more flip-flops but less decoding circuitry

D a johnson counter has an inverted feedback path

Q8: What is a shift register that will accept a parallel input and can shift data left or right called?

A tri-state

B end around

C bidirectional universal

D conversion

Q9: What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?

A The output word decreases by 1.

B The output word decreases by 2.

C The output word increases by 1.

D The output word increases by 2.

Q10: When the output of a tri-state shift register is disabled, the output level is placed in a:

A float state

B LOW state

C high impedance state

D float state and a high impedance state

Q11: What is meant by parallel-loading the register?

A Shifting the data in all flip-flops simultaneously

B Loading data in two of the flip-flops

C Loading data in all four flip-flops at the same time

D Momentarily disabling the synchronous SET and RESET inputs

Q12: To operate correctly, starting a ring counter requires:

A clearing all the flip-flops

B presetting one flip-flop and clearing all the others

C clearing one flip-flop and presetting all the others

D presetting all the flip-flops

Q13: One of the major drawbacks to the use of asynchronous counters is that:

A low-frequency applications are limited because of internal propagation delays

B high-frequency applications are limited because of internal propagation delays

C Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.

D Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications.

Q14: Mod-6 and mod-12 counters are most commonly used in:

A frequency counters

B multiplexed displays

C digital clocks

D power consumption meters


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