A a
B b
C c
D d

A XOR
B XNOR
C XAND
D XNAND

# Q3: As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have taken several readings at numerous IC chips, but the readings are inconclusive because of their erratic nature. Of the possible faults listed, select the one that most probably is causing the problem.

A A defective IC chip that is drawing excessive current from the power supply
B A solar bridge between the inputs on the first IC chip on the board
C An open input on the first IC chip on the board
D A defective output IC chip that has an internal open to Vcc

# Q4: A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong?

A The output of the gate appears to be open.
B The dim indication on the logic probe indicates that the supply voltage is probably low.
C The dim indication is a result of a bad ground connection on the logic probe.
D The gate may be a tristate device.

# Q5: What will a design engineer do after he/she is satisfied that the design will work?

A Put it in a flow chart
B Program a chip and test it
C Give the design to a technician to verify the design
D Perform a vector test

A a
B b
C c
D d

A  = 0, Cout = 0
B  = 0, Cout = 1
C  = 1, Cout = 0
D  = 1, Cout = 1

A 1110010
B 1111001
C 110010
D 001101

# Q9:For the device shown here, assume the D input is LOW, both S inputs are LOW, and the input is LOW. What is the status of the outputs?

A All are HIGH.
B All are LOW.
C All but  are LOW.
D All but  are HIGH.

A a
B b
C c
D d

# Q11:The device shown here is most likely a ________.

A comparator
B multiplexer
C demultiplexer
D parity generator

A 3
B 4
C 5
D 6

# Q13: The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

A A > B = 1, A < B = 0, A < B = 1
B A > B = 0, A < B = 1, A = B = 0
C A > B = 1, A < B = 0, A = B = 0
D A > B = 0, A < B = 1, A = B = 1

A 1111110
B 1111101
C 1111000
D 1111111

A (A + B)(C + D)
B (AB)(CD)
C AB(CD)
D AB + CD

A
B
C
D

# Q17: Which of the following combinations of logic gates can decode binary 1101?

A One 4-input AND gate
B One 4-input AND gate, one OR gate
C One 4-input NAND gate, one inverter
D One 4-input AND gate, one inverter

A
B
C
D

# Q19:The device shown here is most likely a ________.

A comparator
B multiplexer
C demultiplexer
D parity generator

A a
B b
C c
D d

# Q21: What is the indication of a short on the input of a load gate?

A Only the output of the defective gate is affected.
B There is a signal loss to all gates on the node.
C The affected node will be stuck in the LOW state.
D There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state.

A AND/OR
B NAND
C NOR
D OR/AND

A A + BC + D
B ((A + B)C) + D
C D(A + B + C)
D (AC + BC)D

# Q24: Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input is 1. What are the values for the sum and carry output?

A 4321 = 0111, Cout = 0
B 4321 = 1111, Cout = 1
C 4321 = 1011, Cout = 1
D 4321 = 1100, Cout = 1

A 10101
B 10010
C 10001
D 11000

A Current tracer
B Logic probe
C Oscilloscope
D Logic analyzer

A a
B b
C c
D d

# Q28:For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is HIGH. What is the status of the outputs?

A All are HIGH.
B All are LOW.
C All but  are LOW.
D All but  are HIGH.

A 1
B 2
C 4
D 8

# Q30:For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be HIGH. What is the status of the Y output?

A LOW
B HIGH
C Don't Care
D Cannot be determined

# Q31: Which of the following statements accurately represents the two BEST methods of logic circuit simplification?

A Boolean algebra and Karnaugh mapping
B Karnaugh mapping and circuit waveform analysis
C Actual circuit trial and error evaluation and waveform analysis
D Boolean algebra and actual circuit trial and error evaluation

A (A + B)(C + D)
B (AB)(CD)
C AB(CD)
D AB + CD

# Q33: A decoder can be used as a demultiplexer by ________.

A tying all enable pins LOW
B tying all data-select lines LOW
C tying all data-select lines HIGH
D using the input lines for data selection and an enable line for data input

# Q34:For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW. What is the status of the Y output?

A LOW
B HIGH
C Don't Care
D Cannot be determined

# Q35: In HDL, LITERALS is/are:

A digital systems.
B scalars
C binary coded decimals.
D a numbering system.

# Q36: The design concept of using building blocks of circuits in a PLD program is called a(n):

A hierarchical design.
B architectural design.
C digital design.
D verilog.

A
B
C
D

A 5
B 6
C 7
D 8

A 1
B 2
C 3
D 4

# Q40: Which statement below best describes a Karnaugh map?

A A Karnaugh map can be used to replace Boolean rules.
B The Karnaugh map eliminates the need for using NAND and NOR gates.
C Variable complements can be eliminated by using Karnaugh maps.
D Karnaugh maps provide a visual approach to simplifying Boolean expressions.

# Q41: In VHDL, macrofunctions is/are:

A digital circuits.
B analog circuits.
C a set of bit vectors.
D preprogrammed TTL devices.

# Q42:Based on the indications of probe A in the figure given below, what is wrong, if anything, with the circuit?

A The logic probe is unable to determine the state of the circuit at that point and is blinking to alert the technician to the problem.
B The output appears to be shorted to Vcc, but is being pulsed by the pulser.
C The output appears to be LOW, but is being pulsed by the pulser.
D Nothing appears to be wrong at that point.

A NOR
B OR
C Exclusive-OR
D AND

# Q44: Which of the following is an important feature of the sum-of-products form of expressions?

A All logic circuits are reduced to nothing more than simple AND and OR operations.
B The delay times are greatly reduced over other forms.
C No signal must pass through more than two gates, not including inverters.
D The maximum number of gates that any signal must pass through is reduced by a factor of two.

# Q45: What is the indication of a short to ground in the output of a driving gate?

A Only the output of the defective gate is affected.
B There is a signal loss to all load gates.
C The node may be stuck in either the HIGH or the LOW state.
D The affected node will be stuck in the HIGH state.

A Cp = AB
B Cp = A + B
C
D

# Q47: Looping on a K-map always results in the elimination of:

A variables within the loop that appear only in their complemented form.
B variables that remain unchanged within the loop.
C variables within the loop that appear in both complemented and uncomplemented form.
D variables within the loop that appear only in their uncomplemented form.

# Q48: A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes LOW when the inputs are 1001?

A 0
B 3
C 9
D None. All outputs are HIGH.

# Q49: Each "1" entry in a K-map square represents:

A a HIGH for each input truth table condition that produces a HIGH output.
B a HIGH output on the truth table for all LOW input combinations.
C a LOW output for all possible HIGH input conditions.
D a DON'T CARE condition for all possible input truth table combinations.

# Q50: How many data select lines are required for selecting eight inputs?

A 1
B 2
C 3
D 4

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