Counters

Q1: A reliable method for eliminating decoder spikes is to use strobing.

A
True

B
False

Q2: Basic counters can be cascaded in parallel to increase the number of data bits that the counter can handle.

A
True

B
False

Q3: To cascade is to connect in parallel.

A
True

B
False

Q4: Dependency notation is no longer used.

A
True

B
False

Q5: In many cases, counters must be strobed in order to eliminate glitches.

A
True

B
False

Q6: One characteristic of a ring counter is that the modulus is equal to the number of flip-flops in the register and, consequently, there are never any unused or invalid states.

A
True

B
False

Q7: All flip-flops in an asynchronous counter change states at the same time.

A
True

B
False

Q8: The serial in/parallel out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.

A
True

B
False

Q9: The MOD number of a Johnson counter will always be equal to one-half the number of flip-flops in the counter.

A
True

B
False

Q10: A state diagram is a table of states.

A
True

B
False

Q11: A J-K flip-flop excitation table lists the present state, the next state, and the J and K levels required to produce each transition.

A
True

B
False

Q12: Synchronous binary counters can only be used for the application of timing of digital systems.

A
True

B
False

Q13: Bidirectional shift registers can shift data either right or left.

A
True

B
False

Q14: The terminal count of a typical modulus-10 binary counter is 1010.

A
True

B
False

Q15: The modulus of a counter is the actual number of states in its sequence.

A
True

B
False

Q16: In a seven-segment LED display, the BCD must be decoded into a format that can be used to drive the decimal numeric display.

A
True

B
False

Q17: A glitch is a short pulse resulting in an undesired result in a digital circuit.

A
True

B
False

Q18: All decade counters are BCD counters.

A
True

B
False

Q19: To cascade is to connect in parallel.

A
True

B
False

Q20: A serial in/serial out shift register transfers data from one line of a parallel bus to another line one bit at a time.

A
True

B
False

Q21: Shift register counters use logic functions to reset the registers when the desired count is reached.

A
True

B
False

Q22: An asynchronous counter differs from a synchronous counter in the method of clocking.

A
True

B
False

Q23: To design a divide-by-200 counter using synchronous counters, two 4-bit counters could be cascaded together to form an 8-bit counter.

A
True

B
False

Q24: A parallel in/serial out shift register enters all data bits simultaneously and transfers them out one bit at a time.

A
True

B
False

Q25: Shift registers are used to store and transfer data.

A
True

B
False

Q26: In a full-featured counter in HDL, the concept of rolling over simply means the count sequence has reached its limit and must start over at the beginning of the sequence.

A
True

B
False

Q27: In a 74192 BCD decade up-/down-counter, the terminal count up and the terminal count down are active-LOW.

A
True

B
False

Q28: The 7447 has a 4-bit BCD input, seven individual active-LOW outputs, and a ripple blanking input and output.

A
True

B
False

Q29: Three cascaded modulus-10 counters have an overall modulus of 1000.

A
True

B
False

Q30: Counters are generally decoded in order to determine their count state.

A
True

B
False

Q31: Phototransistors have varying resistance from collector to emitter, depending on how much light strikes them.

A
True

B
False

Q32: The concept of a counter to implement a digital one-shot using HDL is not used.

A
True

B
False

Q33: An effective time delay device can be constructed by using the propagation delay characteristic of parallel shift registers.

A
True

B
False

Q34: Parallel in/parallel out registers have parallel input and output busses.

A
True

B
False

Q35: In VHDL, when we want to remember a value it must be stored in a VARIABLE.

A
True

B
False

Q36: Most sequential circuits contain a combinational logic section and a memory section.

A
True

B
False

Q37: Once an up/down counter begins its count sequence, it cannot be reversed.

A
True

B
False

Q38: The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.

A
True

B
False

Q39: Another term used to describe up/down counters is bidirectional.

A
True

B
False

Q40: A ripple counter is an asynchronous counter.

A
True

B
False

Q41: The terminal marked A on the CTR block in the given figure is the SET terminal.

A
True

B
False

Q42: Cascade means to connect the Q output of one flip-flop to the clock input of the next.

A
True

B
False

Q43: When implementing a complete system application using IC counter chips, output devices such as LED indicators must be configured to operate from the counter outputs.

A
True

B
False

Q44: The term synchronous refers to events that do not occur at the same time.

A
True

B
False

Q45: In a synchronous counter, each state is clocked by the same pulse.

A
True

B
False

Q46: Asynchronous counters are known as modulus counters.

A
True

B
False

Q47: When a J-K flip-flop is used in a circuit, we only have to consider the level at J and K at the active clock edge to know the states of the outputs.

A
True

B
False

Q48: Generally speaking, the synchronous counter requires more circuitry than an asynchronous counter.

A
True

B
False


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