Digital Arithmetic Operations and Circuits

Q1: When multiplying 13 × 11 in binary, what is the third partial product?

A 1011

B 00000000

C 100000

D 100001

Q2:
Divide the following binary numbers.

A 0000  0010    0000  0010    1000  1111

B 0000  0010    0001  0010    0000  0100

C 0000  0011    0000  0010    0000  0100

D 0000  0010    0000  0010    0000  0100

Q3: When 1100010 is divided by 0101, what is the decimal remainder?

A 2

B 3

C 4

D 6

Q4:
Convert each of the decimal numbers to 8-bit two's-complement form and then perform subtraction by taking the two's-complement and adding.

A 0001  0011

B 0000  1110

C 0010  1110

D 1110  0000

Q5: How many basic binary subtraction operations are possible?

A 4

B 3

C 2

D 1

Q6: What distinguishes the look-ahead-carry adder?

A It is slower than the ripple-carry adder.

B It is easier to implement logically than a full adder.

C It is faster than a ripple-carry adder.

D It requires advance knowledge of the final answer.

Q7: Solve this BCD problem: 0100 + 0110 =

A 00010000BCD

B 00010111BCD

C 00001011BCD

D 00010011BCD

Q8: The carry propagation delay in 4-bit full-adder circuits:

A is cumulative for each stage and limits the speed at which arithmetic operations are performed

B is normally not a consideration because the delays are usually in the nanosecond range

C decreases in direct ratio to the total number of full-adder stages

D increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations

Q9: The decimal value for E16 is:

A 1210

B 1310

C 1410

D 1510

Q10: How many inputs must a full-adder have?

A 2

B 3

C 4

D 5

Q11:
The truth table for a full adder is shown below. What are the values of X, Y, and Z?

A X = 0, Y = 1, Z = 1

B X = 1, Y = 1, Z = 1

C X = 1, Y = 0, Z = 1

D X = 0, Y = 0, Z = 1

Q12: The BCD addition of 910 and 710 will give initial code groups of 1001 + 0111. Addition of these groups generates a carry to the next higher position. The correct solution to this problem would be to:

A ignore the lowest order code group because 0000 is a valid code group and prefix the carry with three zeros

B add 0110 to both code groups to validate the carry from the lowest order code group

C disregard the carry and add 0110 to the lowest order code group

D add 0110 to the lowest order code group because a carry was generated and then prefix the carry with three zeros

Q13: An 8-bit register may provide storage for two's-complement codes within which decimal range?

A +128 to –128

B –128 to +127

C +128 to –127

D +127 to –127

Q14: Solve this binary problem: 01110010 – 01001000 =

A 00011010

B 00101010

C 01110010

D 00111100

Q15:
Convert each of the following signed binary numbers (two's-complement) to a signed decimal number.
00000101        11111100        11111000

A –5    +4    +8

B +5    –4    –8

C –5    +252    +248

D +5    –252    –248

Q16:
Add the following BCD numbers.
0110   0111   1001
0101   1000   1000

A 0000  1011    0000  1111    0001  0001

B 0001  0001    0001  0101    0001  0001

C 0000  1011    0000  1111    0001  0111

D 0001  0001    0001  0101    0001  0111

Q17: An input to the mode pin of an arithmetic/logic unit (ALU) determines if the function will be:

A one's-complemented

B arithmetic or logic

C positive or negative

D with or without carry

Q18: Fast-look-ahead carry circuits found in most 4-bit full-adder circuits:

A determine sign and magnitude

B reduce propagation delay

C add a 1 to complemented inputs

D increase ripple delay

Q19: Using 4-bit adders to create a 1See Section 6-bit adder:

A requires 16 adders.

B requires 4 adders.

C requires the carry-out of the less significant adder to be connected to the carry-in of the next significant adder.

D requires 4 adders and the connection of the carry out of the less significant adder to the carry-in of the next significant adder.

Q20: What is the first thing you will need if you are going to use a macrofunction?

A A complicated design project

B An experienced design engineer

C Good documentation

D Experience in HDL

Q21: The most commonly used system for representing signed binary numbers is the:

A 2's-complement system.

B 1's-complement system.

C 10's-complement system.

D sign-magnitude system.

Q22:
What is wrong, if anything, with the circuit in the given figure based on the logic analyzer display accompanying the circuit?

A The CO terminal is shorted to ground.

B The S1 output is shorted to Vcc.

C The P1 input is not being added into the total.

D Nothing is wrong; the circuit is functioning correctly.

Q23: How many inputs must a full-adder have?

A 4

B 2

C 5

D 3

Q24:
Convert each of the decimal numbers to two's-complement form and perform the addition in binary.
+13 –10
add –7 add +15

A 0001  0100    0000  0101

B 0000  0110    0001  1001

C 0000  0110    0000  0101

D 1111  0110    1111  0101

Q25: The carry propagation delay in full-adder circuits:

A is normally not a consideration because the delays are usually in the nanosecond range.

B decreases in a direct ratio to the total number of FA stages.

C is cumulative for each stage and limits the speed at which arithmetic operations are performed.

D increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations.

Q26:
Add the following hexadecimal numbers.
3C   14   3B
+25   +28   +DC

A 60    3C    116

B 62    3C    118

C 61    3C    117

D 61    3D    117

Q27: The 2's-complement system is to be used to add the signed binary numbers 11110010 and 11110011. Determine, in decimal, the sign and value of each number and their sum.

A –113 and –114, –227

B –14 and –13, –27

C –11 and –16, –27

D –27 and –13, –40

Q28: Find the 2's complement of –1101102.

A 1101002

B 1010102

C 0010012

D 0010102

Q29: One way to make a four-bit adder perform subtraction is by:

A inverting the output.

B inverting the carry-in.

C inverting the B inputs.

D grounding the B inputs.

Q30: Which of the following is correct for full adders?

A Full adders have the capability of directly adding decimal numbers.

B Full adders are used to make half adders.

C Full adders are limited to two inputs since there are only two binary digits.

D In a parallel full adder, the first stage may be a half adder.

Q31: Solving –11 + (–2) will yield which two's-complement answer?

A 1110 1101

B 1111 1001

C 1111 0011

D 1110 1001

Q32: If B[7..0] = 10100101, what is the value of B[6..2]?

A 10100

B 01001

C 10010

D 00101

Q33: What is the most important operation in binary-coded decimal (BCD) arithmetic?

A addition

B subtraction

C multiplication

D division

Q34: What is one disadvantage of the ripple-carry adder?

A The interconnections are more complex.

B More stages are required to a full adder.

C It is slow due to propagation time.

D All of the above.

Q35:
Add the following binary numbers.
0010 0110   0011 1011   0011 1100
+0101 0101   +0001 1110   +0001 1111

A 0111 1011    0100  0001    0101  1011

B 0111 1011    0101  1001    0101  1011

C 0111 0111    0101  1001    0101  1011

D 0111 0111    0100  0001    0101  1011

Q36: Perform the following hex subtraction: ACE16 – 99916 =

A 23516

B 13516

C 03516

D 33516

Q37: How many BCD adders would be required to add the numbers 97310 + 3910?

A 3

B 4

C 5

D 6

Q38:

A 10011110

B 01211110

C 000100000100

D 001000001000

Q39: What logic function is the sum output of a half-adder?

A AND

B exclusive-OR

C exclusive-NOR

D NAND

Q40:
Subtract the following binary numbers.
0101 1000   1010 0011   1101 1110
–0010 0011   –0011 1000   –0101 0111

A 0011  0100    0110  1010    1000  0110

B 0011  0101    0110  1011    1000  0111

C 0011  0101    0110  1010    1000  0111

D 0011  0101    0110  1010    1000  0110

Q41: The two's-complement system is to be used to add the signed numbers 11110010 and 11110011. Determine, in decimal, the sign and value of each number and their sum.

A –14 and –13, –27

B –113 and –114, 227

C –27 and –13, 40

D –11 and –16, –27

Q42: Add the following hex numbers: 011016 + 1001016

A 1012016

B 1002016

C 1112016

D 0012016

Q43:
Multiply the following binary numbers.
1010   1011   1001
×0011   ×0111   ×1010

A 0001  1110    0100  1101    0101  1011

B 0001  1110    0100  1100    0101  1010

C 0001  1110    0100  1101    0101  1010

D 0001  1101    0100  1101    0101  1010

Q44: The binary subtraction 0 – 0 =

A difference = 0
borrow = 0

B difference = 1
borrow = 0

C difference = 1
borrow = 1

D difference = 0
borrow = 1

Q45: What is the major difference between half-adders and full-adders?

A Nothing basically; full-adders are made up of two half-adders.

B Full adders can handle double-digit numbers.

C Full adders have a carry input capability.

D Half adders can handle only single-digit numbers.

Q46: If [A] = 1011 1010, [B] = 0011 0110, and [C] = [A] • [B], what is [C 4..2] in decimal?

A 1

B 2

C 3

D 4

Q47: Convert the decimal numbers 275 and 965 to binary-coded decimal (BCD) and add. Select the BCD code groups that reflect the final answer.

A 1101 1110 1010

B 1110 1010 1110

C 0001 0010 0100 0000

D 0010 0011 0100 0000

Q48:
Solve this binary problem:

A 11001001

B 10010000

C 01101110

D 01110110

Q49: Adding in binary, a decimal 26 + 27 will produce a sum of:

A 111010

B 110110

C 110101

D 101011

Q50: Half-adders can be combined to form a full-adder with no additional gates.

A True

B False

Q51:
Perform subtraction on each of the following binary numbers by taking the two's-complement of the number being subtracted and then adding it to the first number.
01001        01100
00011        00111

A 01100    10011

B 00110    00101

C 10110    10101

D 00111    00100

Q52: A half-adder circuit would normally be used each time a carry input is required in an added circuit.

A True

B False

Q53: The selector inputs to an arithmetic/logic unit (ALU) determine the:

A selection of the IC

B arithmetic or logic function

C data word selection

D clock frequency to be used

Q54: A full-adder adds ________.

A two single bits and one carry bit

B two 2-bit binary numbers

C two 4-bit binary numbers

D two 2-bit numbers and one carry bit

Q55: Could the sum output of a full-adder be used as a two-bit parity generator?

A Yes

B No

Q56:
Determine the two's-complement of each binary number.
00110        00011        11101

A 11001    11100    00010

B 00111    00010    00010

C 00110    00011    11101

D 11010    11101    00011

Q57:
Convert each of the signed decimal numbers to an 8-bit signed binary number (two's-complement).
+7        –3        –12

A 0000  0111    1111  1101    1111  0100

B 1000  0111    0111  1101    0111  0100

C 0000  0111    0000  0011    0000  1100

D 0000  0111    1000  0011    1000  1100

Q58: Solve this binary problem: 01000110 ÷ 00001010 =

A 0111

B 10011

C 1001

D 0011

Q59: The binary adder circuit is designed to add ________ binary numbers at the same time.

A 2

B 4

C 6

D 8

Q60:
Subtract the following hexadecimal numbers.
47   34   FA
–25   –1C   –2F

A 22    18    CB

B 22    17    CB

C 22    19    CB

D 22    18    CC

Q61: What are constants in VHDL code?

A Fixed numbers represented by a name

B Fixed variables used in functions

C Fixed number types

D Constants do not exist in VHDL code.

Q62: What are the two types of basic adder circuits?

A sum and carry

B half-adder and full-adder

C asynchronous and synchronous

D one- and two's-complement

Q63: In VHDL, what is a GENERATE statement?

A The start statement of a program

B Not used in VHDL or ADHL

C A way to get the computer to generate a program from a circuit diagram

D A way to tell the compiler to replicate several components

Q64: Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?

A to decrease the cost

B to make it smaller

C to slow down the circuit

D to speed up the circuit

Q65:
Solve this binary problem:

A 1001

B 0110

C 0111

D 0101

Q66: Binary subtraction of a decimal 15 from 43 will utilize which two's complement?

A 101011

B 110000

C 011100

D 110001

Q67: For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is:

A the same as if the carry-in is tied LOW since the least significant carry-in is ignored.

B that carry-out will always be HIGH.

C a one will be added to the final result.

D the carry-out is ignored.

Q68:
Which of the statements below best describes the given figure?

A Half-carry adder; Sum = 0, Carry = 1

B Half-carry adder; Sum = 1, Carry = 0

C Full-carry adder; Sum = 1, Carry = 0

D Full-carry adder; Sum = 1, Carry = 1

Q69: When performing subtraction by addition in the 2's-complement system:

A the minuend and the subtrahend are both changed to the 2's-complement.

B the minuend is changed to 2's-complement and the subtrahend is left in its original form.

C the minuend is left in its original form and the subtrahend is changed to its 2's-complement.

D the minuend and subtrahend are both left in their original form.

Q70: The range of positive numbers when using an eight-bit two's-complement system is:

A 0 to 64

B 0 to 100

C 0 to 127

D 0 to 256

Q71: What is the difference between a full-adder and a half-adder?

A Half-adder has a carry-in.

B Full-adder has a carry-in.

C Half-adder does not have a carry-out.

D Full-adder does not have a carry-out.

Q72: Which of the following is the primary advantage of using binary-coded decimal (BCD) instead of straight binary coding?

A Fewer bits are required to represent a decimal number with the BCD code.

B BCD codes are easily converted from decimal.

C the relative ease of converting to and from decimal

D BCD codes are easily converted to straight binary codes.

Q73:
What is the correct output of the adder in the given figure, with the outputs in the order:

A 10111

B 11101

C 01101

D 10011

Q74: The summing outputs of a half- or full-adder are designated by which Greek symbol?

A omega

B theta

C lambda

D sigma


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