Q1: In the digital clock project, what is the frequency of the MOD-6 counter in the minutes section?

A
1 pulse per minute
B
6 pulse per minute
C
10 pulse per minute
D
1 pulse per hour

Q2: What are two ways to remember the current state of a counter in VHDL?

A
With FUNCTIONS and PROCESS
B
With counters and timers
C
With SIGNAL and VARIABLE
D
With bit types

A
Clear
B
Enable
C
Reset
D
Store

Q4: How is the output frequency related to the sampling interval of a frequency counter?

A
Directly with the sampling interval
B
Inversely with the sampling interval
C
More precision with longer sampling interval
D
Less precision with longer sampling interval

Q5: In the keypad application, what does the preset state of the ring counter define?

A
The proper output of the column encoder
B
The NANDing of the rows
C
The NANDing of the columns
D
The proper output of the row encoder

A
1 Hz.
B
60 Hz.
C
100 Hz.
D
1000 Hz.

Q7: In the digital clock project, the purpose of the frequency prescaler is to:

A
find the basic frequency.
B
transform a 60 pps input to a 1 pps timing signal.
C
prevent the clock from exceeding 12:59:59.
D
allow the BCD display to have a value from 00–59.

Q8: In an HDL stepper motor design, why is there more than one mode?

A
To change the speed of the stepper motor
B
To change the direction of the stepper motor
C
To direct drive the stepper motor
D
All of the above

Q9: In a frequency counter, what happens at high frequencies when the sampling interval is too long?

A
The counter works fine.
B
The counter undercounts the frequency.
C
The measurement is less precise.
D
The counter overflows.

A
On
B
Off
C
Hi-Z
D
1011

Q11: In the digital clock project, when does the PM indicator go high?

A
Never
B
Going from 11:59:59 to 12:00:00
C
Going from 12:59:59 to 01:00:00
D
On the falling edge of the clock after enable goes high

Q12: Which is not a step in strategic planning for HDL development?

A
There must be a way to test each piece.
B
Each block must fit together to make up the whole system.
C
The names of each input and output must be known.
D
The exact operation of each block must be thoroughly defined and understood.

Q13: In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?

A
It goes HIGH.
B
It goes LOW.
C
It goes to Hi-Z.
D
It goes to 1111H.

Q14: Which is not a major block of an HDL frequency counter?

A
Display register
B
Decoder/display
C
Timing and control unit
D
Bit shifter

A
A sequencer
B
A clock
C
A multiplexer
D
A ring counter

A
6
B
5
C
4
D
3

Q17: In an HDL application of a stepper motor, after an up/down counter is built what is done next?

A
Build the sequencer
B
Test it on a simulator
C
Test the decoder
D
Design an intermediate integer variable

Q18: Which is not a step used to define the scope of an HDL project?

A
Are the inputs and outputs active HIGH or active LOW?
B
A clear vision of how to make each block work
C
What are the speed requirements?
D
How many bits of data are needed?

Q19: In the digital clock project, what type of counter is used to count to 59 seconds?

A
MOD-60
B
MOD-6
C
BCD
D
BCD followed by a MOD-6

Q20: The accuracy of the frequency counter depends on the:

A
system clock frequency.
B
number of displayed digits.
C
sampling rate.
D
display update rate.

Q21: In the frequency counter, when is the new count stored in the display register?

A
After disabling the counter
B
When the count buffer is full
C
After the sample interval is set
D
When the timing and control block has put it there

A
90°
B
45°
C
30°
D
15°

Q23: In the frequency counter, what is the function of the Schmitt trigger circuit?

A
To reduce input noise
B
To condition the input signal
C
To convert non-square waveforms
D
To provide a usable signal to the display unit

Q24: Which is not a step that should be followed in project management?

A
Overall definition
B
System documentation
C
Synthesis and testing
D
System integration

Q25: What does the ring counter in the HDL keypad application do when a key is pressed?

A
Count to find the row
B
Freeze
C
Count to find the column
D
Start the D flip-flop

Q26: Why should a real hardware functional test be performed on the HDL stepper motor design?

A
To check the speed of the software
B
To check the current levels in the motor
C
To check the voltage levels of the real outputs
D
To provide a fully operational system

Q27: Why should a real hardware functional test be performed on the HDL stepper motor design?

A
To check the speed of the software
B
To check the current levels in the motor
C
To check the voltage levels of the real outputs
D
To provide a fully operational system

Q28: What must a stepper motor HDL application include?

A
Variables and processes
B
Types and bits
C
Counters and decoders
D
Sequencers and multiplexers

Q29: List three basic blocks in the digital clock project.

A
MOD-60, MOD-12 counters
B
MOD-5, MOD-10, MOD-12 counters
C
MOD-60, MOD-10 counters
D
MOD-6, MOD-12, and MOD-10 counters

Q30: In the keypad application, what does the data signal define?

A
The row and column encoded data
B
The ring encoded data
C
The freeze locator data
D
The ring counter data

Q31: When designing an HDL digital system, which is the worst mistake one can make?

A
Concluding that a fundamental block works perfectly
B
Failing to provide proper documentation
C
Adding blocks of code prior to testing them
D
Overlooking a possible VARIABLE

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