Memory and Storage

Q1: Why is a refresh cycle necessary for a dynamic RAM?

A to clear the flip-flops

B to set the flip-flops

C The refresh cycle discharges the capacitor cells.

D The refresh cycle keeps the charge on the capacitor cells.

Q2: How many address lines would be required for a 2K × 4 memory chip?

A 8

B 10

C 11

D 12

Q3: What is the maximum time required before a dynamic RAM must be refreshed?

A 2 ms

B 4 ms

C 8 ms

D 10 ms

Q4: The storage element for a static RAM is the ________.

A diode

B resistor

C capacitor

D flip-flop

Q5: Information that is stored in an EEPROM ________.

A can be modified by performing a memory write operation

B is stored by the manufacturer and cannot be changed

C is lost if power is interrupted

D can be erased by applying high voltage to each storage location

Q6: The main advantage of semiconductor RAM is its ability to:

A retain stored data when power is interrupted or turned off

B be written to and read from rapidly

C be randomly accessed

D be sequentially accessed

Q7: What is the principal advantage of using address multiplexing with DRAM memory?

A reduced memory access time

B reduced requirement for constant refreshing of the memory contents

C reduced pin count and decrease in package size

D It eliminates the requirement for a chip-select input line, thereby reducing the pin count.

Q8: Which of the following is one of the basic characteristics of DRAMs?

A DRAMs must have a constantly changing input.

B DRAMs must be periodically refreshed in order to be able to retain data.

C DRAMs have a broader "dynamic" storage range than other types of memories.

D DRAMs are simpler devices than other types of memories.

Q9: What is the difference between static RAM and dynamic RAM?

A Static RAM must be refreshed, dynamic RAM does not.

B There is no difference.

C Dynamic RAM must be refreshed, static RAM does not.

Q10: To which pin on the RAM chip does the address decoder connect in order to signal which memory chip is being accessed?

A The address input

B The output enable

C The chip enable

D The data input

Q11: How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits?

A Eight

B Four

C Two

D One

Q12: Why are ROMs called nonvolatile memory?

A They lose memory when power is removed.

B They do not lose memory when power is removed.

Q13: What is the meaning of RAM, and what is its primary role?

A Readily Available Memory; it is the first level of memory used by the computer in all of its operations.

B Random Access Memory; it is memory that can be reached by any sub- system within a computer, and at any time.

C Random Access Memory; it is the memory used for short-term temporary data storage within the computer.

D Resettable Automatic Memory; it is memory that can be used and then automatically reset, or cleared, after being read from or written to.

Q14:
For the given circuit, what is the bit length of the output data word?

A 3

B 4

C 8

D 32

Q15: The periodic recharging of DRAM memory cells is called ________.

A multiplexing

B bootstrapping

C refreshing

D flashing

Q16: How many 1K × 4 RAM chips would be required to build a 1K × 8 memory system?

A 2

B 4

C 8

D 16

Q17: The time from the beginning of a read cycle to the end of tACS or tAA is referred to as:

A access time

B data hold

C read cycle time

D write enable time

Q18: Select the statement that best describes the fusible-link PROM.

A user-programmable, one-time programmable

B manufacturer-programmable, one-time programmable

C user-programmable, reprogrammable

D manufacturer-programmable, reprogrammable

Q19: Which of the following is NOT a type of memory?

A RAM

B ROM

C FPROM

D EEPROM

Q20: Address decoding for dynamic memory chip control may also be used for:

A controlling refresh circuits

B read and write control

C chip selection and address location

D memory mapping

Q21: How many address bits are needed to select all memory locations in the 2118 16K × 1 RAM?

A 8

B 10

C 14

D 16

Q22: ROMs retain data when the ________.

A power is off

B power is on

C system is down

D all of the above

Q23: What is the bit storage capacity of a ROM with a 1024 × 8 organization?

A 1024

B 2048

C 4096

D 8192

Q24: What does the term "random access" mean in terms of memory?

A Addresses must be accessed in a specific order.

B Any address can be accessed in any order.

Q25: FIFO is formed by an arrangement of ________.

A diodes

B transistors

C MOS cells

D shift registers

Q26:
For the given circuit, which of the following is correct?

A The number 5 is being written to the memory at address location 203.

B The chip has not been enabled, since the EN terminal is 0; therefore, nothing will be written to the chip and the output is tri-stated.

C Decimal 10 is being written into memory location 211.

D The read/write line is LOW; therefore, decimal 5 is being stored at memory location 211.

Q27: The refresh period for capacitors used in DRAMs is ________.

A 2 ms

Bs

C 64 ms

D 64 s

Q28:
Refer the given figure. The outputs (Q0–Q3) of the memory are always LOW. The address lines (A0–A7) are checked with a logic probe and all are indicating pulse activity, except for A3, which shows a constant HIGH, and A7, which shows a constant LOW; the select lines, are checked and shows pulse activity, while indicates a constant HIGH. What is wrong, and how can the memory be tested to determine whether it is defective or if the external circuitry is defective?

A One of the inputs to the active-LOW select AND gate may be stuck high for some reason; take both select lines LOW and check for pulse activity on the outputs, Q0–Q3. If the outputs now respond, the problem is most likely in the program or circuitry driving the select lines.

B The problem appears to be in the two address lines that never change levels; the problem is probably in the program driving the memory address bus.

C The output buffers are probably defective since they are all tied together; the common input line is most likely stuck LOW. Change the output buffer IC.

D Since no data appears to be getting through to the output buffers, the problem may be in the X decoder; change the X decoder IC.

Q29: Dynamic memory cells store a data bit in a ________.

A diode

B resistor

C capacitor

D flip-flop

Q30: The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is ________.

A 4096

B 8129

C 16358

D 32768

Q31: Which is not a removable drive?

A Zip

B Jaz

C Hard

D SuperDisk

Q32: Which of the following memories is volatile?

A ROM

B EROM

C RAM

D Flash

Q33: In general, the ________ have the smallest bit size and the ________ have the largest.

A EEPROMs, Flash

B SRAM, mask ROM

C mask ROM, SRAM

D DRAM, PROM

Q34: Advantage(s) of an EEPROM over an EPROM is/are:

A the EPROM can be erased with ultraviolet light in much less time than an EEPROM

B the EEPROM can be erased and reprogrammed without removal from the circuit

C the EEPROM has the ability to erase and reprogram individual words

D the EEPROM can be erased and reprogrammed without removal from the circuit, and can erase and reprogram individual words

Q35: Which of the following faults will the checkerboard pattern test for in RAM?

A Short between adjacent cells

B Ability to store both 0s and 1s

C Dynamically introduced errors between cells

D All of the above

Q36: The reason the data outputs of most ROM ICs are tristate outputs is to:

A allow for three separate data input lines.

B allow the bidirectional flow of data between the bus lines and the ROM registers.

C permit the connection of many ROM chips to a common data bus.

D isolate the registers from the data bus during read operations.

Q37: Assume a ROM to be tested is compared with a known good ROM. If the checksums differ, the ROM is ________.

A very likely to be good

B definitely good

C very likely to be bad

D definitely bad

Q38:
What is the significance of the inverted triangles on the outputs of the device in the given figure?

A They represent inverters and mean that the outputs are active-LOW.

B They represent buffers and mean that the outputs can drive 40 TTL loads, instead of the normal 10.

C It means that the outputs will be active only if a change has occurred at that memory location since the last read/write cycle.

D The outputs are tristated.

Q39: Which of the following is not a flash memory mode or operation?

A Burst

B Read

C Erase

D Programming

Q40: Which of the following best describes random-access memory (RAM)?

A a type of memory in which access time depends on memory location

B a type of memory that can be written to only once but can be read from an infinite number of times

C a type of memory in which access time is the same for each memory location

D mass memory

Q41: The difference between RAM and ROM is that ________.

A RAM has a read/write signal and ROM doesn't

B RAM will lose data when the power is removed and ROM won't

C RAM has random address access and ROM uses sequential address access

D RAM has a read/write signal and ROM doesn't; RAM will lose data when the power is removed and ROM won't.

E All of the above

Q42: Which of the following best describes static memory devices?

A memory devices that are magnetic in nature and do not require constant refreshing

B memory devices that are magnetic in nature and require constant refreshing

C semiconductor memory devices in which stored data will not be retained with the power applied unless constantly refreshed

D semiconductor memory devices in which stored data is retained as long as power is applied

Q43: The location of a unit of data in a memory array is called its ________.

A storage

B RAM

C address

D data

Q44: Select the statement that best describes Read-Only Memory (ROM).

A nonvolatile, used to store information that changes during system operation

B nonvolatile, used to store information that does not change during system operation

C volatile, used to store information that changes during system operation

D volatile, used to store information that does not change during system operation

Q45: A major disadvantage of the mask ROM is that it:

A is time consuming to change the stored data when system requirements change

B is very expensive to change the stored data when system requirements change

C cannot be reprogrammed if stored data needs to be changed

D has an extremely short life expectancy and requires frequent replacement

Q46:
The device shown in the given figure is checked with a logic probe and the output is HIGH.

A The device is working properly.

B For the input conditions shown the output should be LOW; the input is shorted to ground.

C For the input conditions shown the output should be neither HIGH nor LOW; the device is shorted to .

D The device is probably alright; the problem is most likely caused by the stage connected to the output of the device.

Q47: Microprocessors and memory ICs are generally designed to drive only a single TTL load. Therefore, if several inputs are being driven from the same bus, any memory IC must be ________.

A buffered

B decoded

C addressed

D stored

Q48: Which is not part of a hard disk drive?

A Spindle

B Platter

C Read/write head

D Valve

Q49: Which is not a magnetic storage device?

A Magnetic disk

B Magnetic tape

C Magneto-optical disk

D Optical disk

Q50: Suppose that a certain semiconductor memory chip has a capacity of 8K × 8. How many bytes could be stored in this device?

A 8,000

B 64,000

C 65,536

D 8,192

Q51: An 8-bit address code can select ________.

A 8 locations in memory

B 256 locations in memory

C 65,536 locations in memory

D 131,072 locations in memory

Q52: Which type of ROM can be erased by an electrical signal?

A ROM

B mask ROM

C EPROM

D EEPROM

Q53: One of the most important specifications on magnetic media is the ________.

A rotation speed

B tracks per inch

C data transfer rate

D polarity reversal rate

Q54: Which of the following best describes EPROMs?

A EPROMs can be programmed only once.

B EPROMs can be erased by UV.

C EPROMs can be erased by shorting all inputs to the ground.

D All of the above.

Q55: What are the typical values of tOE?

A 10 to 20 ns for bipolar

B 25 to 100 ns for NMOS

C 12 to 50 ns for CMOS

D All of the above

Q56: A 64-Mbyte SIMM is installed into a system, but when a memory test is executed, the SIMM is detected as a 32-Mbyte device. What is a possible cause?

A The memory module was not installed properly.

B The voltage on the memory module is incorrect.

C The most significant address line is stuck high or low.

D The address decoder on the SIMM is faulty.

Q57: The mask ROM is ________.

A MOS technology

B diode technology

C resistor-diode technology

D DROM technology

Q58:
The RAM circuit given below is suspected of being bad. A check with a logic probe shows pulse activity on all of the address lines and data inputs. The / line and inputs are forced HIGH and the data output lines are checked with the logic probe. Q0, Q2, and Q3 show a dim indication on the logic probe; Q1 indicates a HIGH level on the logic probe. What, if anything, is wrong with the circuit?

A The Q0, Q2, and Q3 output lines are open; the chip is defective.

B The Q1 line appears to be shorted to Vcc; replace the chip.

C The outputs should be active only when the / line is held LOW, so the circuit is behaving normally considering the fact that the line is HIGH.

D The EN input should be forced HIGH and the outputs rechecked; if they are still giving the same indications as before, then the three outputs are definitely open and the IC will have to be replaced.

Q59: On a CD-ROM, ________ are recessed areas representing a 0.

A mounds

B lands

C holes

D pits

Q60: The condition occurring when two or more devices try to write data to a bus simultaneously is called ________.

A address decoding

B bus contention

C bus collisions

D address multiplexing

Q61: What part of a Flash memory architecture manages all chip functions?

A I/O pins

B floating-gate MOSFET

C command code

D program verify code

Q62: Which of the following describes the action of storing a bit of data in a mask ROM?

A A 1 is stored in a bipolar cell by opening the base connection to the address line.

B A 0 is stored in a bipolar cell by shorting the base connection to the address line.

C A 1 is stored by connecting the gate of a MOS cell to the address line.

D A 0 is stored by connecting the gate of a MOS cell to the address line.

Q63: How can UV erasable PROMs be recognized?

A There is a small window on the chip.

B They will have a small violet dot next to the #1 pin.

C Their part number always starts with a "U", such as in U12.

D They are not readily identifiable, since they must always be kept under a small cover.

Q64: How many storage locations are available when a memory device has 12 address lines?

A 144

B 512

C 2048

D 4096

Q65: Which of the following memories uses a MOS capacitor as its memory cell?

A SRAM

B DRAM

C ROM

D FIFO

Q66: Describe the timing diagram of a write operation.

A First the data is set on the data bus and the address is set, then the write pulse stores the data.

B First the address is set, then the data is set on the data bus, and finally the read pulse stores the data.

C First the write pulse stores the data, then the address is set, and finally the data is set on the data bus.

D First the data is set on the data bus, then the write pulse stores the data, and finally the address is set.

Q67:
For the given circuit, what memory location is being addressed?

A 10111

B 249

C 5

D 157

Q68: Eight bits of digital data are normally referred to as a:

A group.

B byte.

C word.

D cell.

Q69: What is a major disadvantage of RAM?

A Its access speed is too slow.

B Its matrix size is too big.

C It is volatile.

D High power consumption

Q70: CCD stands for ________.

A capacitor charging device

B capacitor-capacitor drain

C charged-capacitor device

D charge-coupled device

Q71: The checkerboard pattern test is used to test ________.

A ROM

B EEPROM

C FPLA

D RAM

Q72: Which of the following best describes volatile memory?

A memory that retains stored information when electrical power is removed

B memory that loses stored information when electrical power is removed

C magnetic memory

D nonmagnetic

Q73: Which type of ROM can be erased by UV light?

A ROM

B mask ROM

C EPROM

D EEPROM

Q74: The ideal memory ________.

A has high storage capacity

B is nonvolatile

C has in-system read and write capacity

D has all of the above characteristics

Q75: What is a multitap digital delay line?

A a series of inverter gates with RC circuits between each one

B a series of inverter gates with RL circuits between each one

C a series of NAND gates with RC circuits between each one

D a series of NAND gates with RL circuits between each one

Q76: A CD-R disk is created by applying heat to special chemicals on the disk and these chemicals reflect less light than the areas that are not burned, thus creating the same effect as a pit does on a regular CD.

A True

B False

Q77: On a CD-ROM, ________ are raised areas representing a 1.

A mounds

B lands

C holes

D pits

Q78: Which of the following RAM timing parameters determine its operating speed?

A tACC

B tAA and tACS

C tCO and tOD

D tRC and tWC

Q79: What is the computer main memory?

A Hard drive and RAM

B CD-ROM and hard drive

C RAM and ROM

D CMOS and hard drive

Q80: The smallest unit of binary data is the ________.

A bit

B nibble

C byte

D word

Q81: Why do most dynamic RAMs use a multiplexed address bus?

A It is the only way to do it.

B to make it faster

C to keep the number of pins on the chip to a minimum

Q82: What is the major difference between SRAM and DRAM?

A DRAMs must be periodically refreshed.

B SRAMs can hold data via a static charge, even with power off.

C The only difference is the terminal from which the data is removed—from the FET Drain or Source.

D Dynamic RAMs are always active; static RAMs must reset between data read/write cycles.

Q83: Typically, how often is DRAM refreshed?

A 2 to 8 ms

B 4 to 16 ms

C 8 to 16 s

D 1 to 2 s

Q84: Which type of ROM has to be custom built by the factory?

A ROM

B mask ROM

C EPROM

D EEPROM

Q85: How many address bits are required for a 4096-bit memory organized as a 512 × 8 memory?

A 2

B 4

C 8

D 9

Q86: How many 2K × 8 ROM chips would be required to build a 16K × 8 memory system?

A 2

B 4

C 8

D 16

Q87: Which is not a hard disk performance parameter?

A Seek time

B Break time

C Latency period

D Access time

Q88: The mask ROM is ________.

A permanently programmed during the manufacturing process

B volatile

C easy to reprogram

D extremely expensive

Q89:
Refer to the given figures (a) and (b). A logic analyzer is used to check the circuit in figure (a) and displays the waveforms shown in figure (b). The actual analyzer display shows all four data outputs, Q0-Q3. The analyzer's cursor is placed at position X and all four of the data output lines show a LOW level output. What is wrong, if anything, with the circuit?

A Nothing is wrong, according to the display. The outputs are in the open state and should show zero output voltage.

B The circuit is in the READ mode and the outputs, Q0-Q3, should reflect the contents of the memory at that address. The chip is defective; replace the chip.

C The circuit is in the  mode and should be writing the contents of the selected address to Q0–Q3.

D The Q0–Q3 lines can be either LOW or HIGH, since the chip is in the tristate mode in which case their level is unpredictable.

Q90: In a DRAM, what is the state of R/W during a read operation?

A Low

B High

C Hi-Z

D None of the above

Q91: Which of the following is normally used to initialize a computer system's hardware?

A Bootstrap memory

B Volatile memory

C External mass memory

D Static memory

Q92: The check sum method of testing a ROM:

A indicates if the data in more than one memory location is incorrect.

B provides a means for locating and correcting data errors in specific memory locations.

C allows data errors to be pinpointed to a specific memory location.

D simply indicates that the contents of the ROM are incorrect.

Q93: Which is/are the basic refresh mode(s) for dynamic RAM?

A Burst refresh

B Distributed refresh

C Open refresh

D Burst refresh and distributed refresh

Q94: EEPROM stands for ________.

A encapsulated electrical programmable read-only memory

B elementary electrical programmable read-only memory

C electrically erasable programmable read-only memory

D elementary erasable programmable read-only memory

Q95: Data is written to and read from the disk via a magnetic ________ head mechanism in the floppy drive.

A cylinder

B read/write

C recordable

D cluster

Q96: What two functions does a DRAM controller perform?

A address multiplexing and data selection

B address multiplexing and the refresh operation

C data selection and the refresh operation

D data selection and CPU accessing

Q97: A 64-bit word consists of ________.

A 4 bytes

B 8 bytes

C 10 bytes

D 12 bytes

Q98: L1 is known as ________.

A primary cache

B secondary cache

C DRAM

D SRAM


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