Shift Registers

Q1: In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns?

A 1

B 2

C 4

D 8

Q2: How much storage capacity does each stage in a shift register represent?

A One bit

B Two bits

C Four bits (one nibble)

D Eight bits (one byte)

Q3: The primary purpose of a three-state buffer is usually:

A to provide isolation between the input device and the data bus

B to provide the sink or source current required by any device connected to its output without loading down the output device

C temporary data storage

D to control data flow

Q4: If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?

A 1101000000

B 0011010000

C 1100000000

D 0000000000

Q5: When is it important to use a three-state buffer?

A when two or more outputs are connected to the same input

B when all outputs are normally HIGH

C when all outputs are normally LOW

D when two or more outputs are connected to two or more inputs

Q6: A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

A ring shift

B clock

C Johnson

D binary

Q7: A 74HC195 4-bit parallel access shift register can be used for ________.

A serial in/serial out operation

B serial in/parallel out operation

C parallel in/serial out operation

D all of the above

Q8: What is meant by parallel load of a shift register?

A All FFs are preset with data.

B Each FF is loaded with data, one at a time.

Q9: To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ________.

A divide-by-4 clock pulse

B sequence generator

C strobe line

D multiplexer

Q10: An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?

A 1.67 s

B 26.67 s

C 26.7 ms

D 267 ms

Q11: By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a ________, ________, and ________-out register.

A parallel-in, serial, parallel

B serial-in, parallel, serial

C series-parallel-in, series, parallel

D bidirectional in, parallel, series

Q12: To operate correctly, starting a ring shift counter requires:

A clearing all the flip-flops

B presetting one flip-flop and clearing all others

C clearing one flip-flop and presetting all others

D presetting all the flip-flops

Q13: Stepper motors have become popular in digital automation systems because ________.

A of their low cost

B they are driven by sequential digital signals

C they can be used to provide repetitive mechanical movement

D they are driven by sequential digital signals and can be used to provide repetitive mechanical movement

Q14: Another way to connect devices to a shared data bus is to use a ________.

A circulating gate

B transceiver

C bidirectional encoder

D strobed latch

Q15: With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________.

A 12 s

B 120 s

C 12 ms

D 120 ms

Q16: In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________.

A 1110

B 0001

C 1100

D 1000

Q17: What does the output enable do on the 74395A chip?

A It determines when data can be loaded.

B It forces all outputs to go HIGH.

C It forces all outputs to go LOW.

D It activates the three-state buffer.

Q18: A modulus-12 ring counter requires a minimum of ________.

A 10 flip-flops

B 12 flip-flops

C 6 flip-flops

D 2 flip-flops

Q19: What is the preset condition for a ring shift counter?

A all FFs set to 1

B all FFs cleared to 0

C a single 0, the rest 1

D a single 1, the rest 0

Q20: An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________.

A 16 s

Bs

Cs

Ds

Q21: The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________.

A 01110

B 00001

C 00101

D 00110

Q22: A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________.

A 0000

B 1111

C 0111

D 1000

Q23: What is the difference between a ring shift counter and a Johnson shift counter?

A There is no difference.

B A ring is faster.

C The feedback is reversed.

D The Johnson is faster.

Q24: When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________.

A 40 kHz

B 50 kHz

C 400 kHz

D 500 kHz

Q25: What is a transceiver circuit?

A a buffer that transfers data from input to output

B a buffer that transfers data from output to input

C a buffer that can operate in both directions

Q26: Which type of device may be used to interface a parallel data format with external equipment's serial format?

A key matrix

B UART

C memory chip

D series in, parallel out

Q27: The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses?

A 0000

B 0010

C 1000

D 1111

Q28: A bidirectional 4-bit shift register is storing the nibble 1101. Its  input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________.

A 1101

B 0111

C 0001

D 1110

Q29: What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called?

A tristate

B end around

C universal

D conversion

Q30: What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?

A parallel-in, parallel-out

B parallel-in, serial-out

C serial-in, parallel-out

D serial-in, serial-out

Q31: When the output of a tristate shift register is disabled, the output level is placed in a:

A float state

B LOW state

C high-impedance state

D float or high-impedance state

Q32: How many clock pulses will be required to completely load serially a 5-bit shift register?

A 2

B 3

C 4

D 5

Q33: In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns?

A 2

B 6

C 12

D 24

Q34: On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3 = 0. On the fourth clock pulse, the sequence is ________.

A Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1

B Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0

C Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0

D Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0

Q35: The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________.

A 10111000

B 10110111

C 11110000

D 11111100

Q36: Computers operate on data internally in a ________ format.

A tristate

B universal

C parallel

D serial

Q37: On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth clock pulse, the sequence is ________.

A Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0

B Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0

C Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1

D Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1

Q38: What are the three output conditions of a three-state buffer?

A HIGH, LOW, float

B 1, 0, float

C both of the above

D neither of the above

Q39: Which is not characteristic of a shift register?

A Serial in/parallel in

B Serial in/parallel out

C Parallel in/serial out

D Parallel in/parallel out

Q40: How can parallel data be taken out of a shift register simultaneously?

A Use the Q output of the first FF.

B Use the Q output of the last FF.

C Tie all of the Q outputs together.

D Use the Q output of each FF.

Q41: To serially shift a nibble (four bits) of data into a shift register, there must be ________.

A one clock pulse

B four clock pulses

C eight clock pulses

D one clock pulse for each 1 in the data

Q42: A bidirectional 4-bit shift register is storing the nibble 1110. Its  input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.

A 1110

B 0111

C 1000

D 1001

Q43: How is a strobe signal used when serially loading a shift register?

A to turn the register on and off

B to control the number of clocks

C to determine which output Qs are used

D to determine the FFs that will be used

Q44: How would a latch circuit be used in a microprocessor system?

A as transportation for Intel employees

B for a group of data that is the same

C as a set of common connections for transfer of data

Q45: What is the function of a buffer circuit?

A to provide an output that is inverted from that on the input

B to provide an output that is equal to its input

C to clean up the input

D to clean up the output

Q46: The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?

A 10011100

B 11000000

C 00001100

D 11110000

Q47: Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

A 1100

B 0011

C 0000

D 1111

Q48: Ring shift and Johnson counters are:

A synchronous counters

B aynchronous counters

C true binary counters

D synchronous and true binary counters

Q49: A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.

A right, one

B right, two

C left, one

D left, three

Q50: What is a recirculating register?

A serial out connected to serial in

B all Q outputs connected together

C a register that can be used over again

Q51: If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?

A 11101011

B 00010111

C 11110000

D 00000000

Q52: What is the difference between a shift-right register and a shift-left register?

A There is no difference.

B the direction of the shift

Q53: With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________.

A 4 μs

B 40 μs

C 400 μs

D 40 ms


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