Counters - Technical MCQs
Q1: In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?A
A trigger edge has occurred and we must load the counter.
B
The counter is zero and we need to keep it at zero.
C
The shift register is reset.
D
The counter is not zero and we need to count down by one.
ANS:C - The shift register is reset. No answer description is available. |
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