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Q1: Referring to the given figure, what causes the Control FF to reset after D7?

A Once the data cycle is initiated by the Start bit, the one-shot produces an output pulse equal to the duration of the eight data bits. Once the eight data bits have been transferred to the data input register, the falling edge of the one-shot pulse resets the Control FF to start the sequence all over again.

B After counting the eight data bits, the divide-by-8 counter produces an output on its active-LOW CLR line to reset the Control FF.

C After counting eight clock pulses equivalent to eight data periods, the terminal count of the divide-by-8 counter and the clock trigger the one-shot, which in turn resets the Control FF and divide-by-8 circuits to begin the sequence all over again. Simultaneously the data is transferred through the output register.

D When the data output register is full, it produces an output on its C terminal that triggers the one-shot, which in turn resets the Control FF.

ANS:C - After counting eight clock pulses equivalent to eight data periods, the terminal count of the divide-by-8 counter and the clock trigger the one-shot, which in turn resets the Control FF and divide-by-8 circuits to begin the sequence all over again. Simultaneously the data is transferred through the output register.

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