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Sequential Logic Circuits

Q1: Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

A input clock pulses are applied only to the first and last stages

B input clock pulses are applied only to the last stage

C input clock pulses are not used to activate any of the counter stages

D input clock pulses are applied simultaneously to each stage

ANS:D - input clock pulses are applied simultaneously to each stage

Any sequential circuit is said to be synchronous if it is driven by the same clock applied at the same time. Whereas it is asynchronous if there are more than one clocks used or the output of one depends on the input of other and the clock is applied only to any one circuit which triggers the other. So asynchronous counters have delay.



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